1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a reduced writing time.
2. Description of the Related Art
Generally, a dynamic random access memory (DRAM) has a longer access time than a static random access memory (SRAM). Thus, the DRAM is generally used to store massive data for its low cost and low power consumption. The SRAM has a short access time, but has demerits of high cost and high power consumption.
Recently, according to development of a system-on-chip (SOC) technology, various circuits, such as a logic circuit and a linear circuit, are included in one semiconductor chip, and a DRAM embedded in the SOC is referred to as an embedded DRAM (EDRAM). The EDRAM has advantages of short access time, low cost and low power consumption. The EDRAM also can be referred to as a Pseudo SRAM (PSRAM) because the EDRAM performs interface operations such that the EDRAM can operate similarly to the SRAM in relation to external circuits.
FIG. 1 is a circuit diagram illustrating a bit line sense amplifier included in the conventional semiconductor memory device.
Referring to FIG. 1, the bit line sense amplifier includes an n-type sense amplifier 40 and a p-type sense amplifier 20 for amplifying a voltage level of data, separation circuits 60 and 70 for separating signals of a memory cell (not shown) from the sense amplifiers 20 and 40, equalization circuits 10 and 50 for pre-charging a bit line BL and a complementary bit line BLB and equalizing a voltage of a bit line BL and a voltage of a complementary bit line BLB, and a column selection circuit 30.
The column selection circuit 30 provides voltage signals of the bit line BL and the complementary bit line BLB to an input/output line pair IOL and IOLB when a column selection signal CSL is enabled in a read mode. The column selection circuit 30 provides voltage signals of the input/output line pair IOL and IOLB to the bit line BL and the complementary bit line BLB when the column selection signal CSL is enabled in a write mode.
Generally, data stored in the memory cell may need to be sensed and restored in writing the data in the memory cell. A data restoring time needs to be reduced in the write mode, particularly in a case of an early write semiconductor memory device. The input/output line pair 10 and IOB is electrically coupled to the bit line pair BL and BLB in the read mode or in a data masking operation mode. Thus, the bit line sense amplifier can have longer restoring time due to a load effect caused by the input/output line pair IO and IOB. The data masking operation means an operation for masking data for preventing the data from being written into some portions of memory cell blocks in a memory cell array. Long restoring time due to the load effect in the masking operation causes an unstable operation and decreases an operation speed of the semiconductor memory device.
Thus, a semiconductor memory device having reduced restoring time of the bit line in the data masking operation mode is required.